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    • 专利摘要:
    A method of producing a semiconductor device (100), comprising the following steps: a) producing, on a substrate (104), a stack comprising a first semiconductor portion capable of forming an active zone and arranged between two second portions of a material capable of being selectively etched with respect to the semiconductor of the first portion, b) forming, on a portion of the stack, external spacers (112) and a dummy grid, c) etching of the second portions such that remaining portions are disposed under the dummy gate, d) partially oxidizing the remaining portions from outer faces, forming internal spacers (118), e) removing the dummy gate and unoxidized portions of the remaining portions disposed under the dummy gate, f) providing a gate (128) between the outer spacers and between the inner spacers and overlying the channel.
    公开号:FR3060840A1
    申请号:FR1662531
    申请日:2016-12-15
    公开日:2018-06-22
    发明作者:Shay REBOH；Emmanuel Augendre；Remi COQUAND
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    Holder (s): COMMISSIONER OF ATOMIC ENERGY AND ALTERNATIVE ENERGIES Public establishment.
    Extension request (s)
    Agent (s): BREVALEX Limited liability company.
    METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERNAL SPACERS.
    FR 3 060 840 - A1 (5 /) Method for producing a semiconductor device (100), comprising the following steps:
    a) production, on a substrate (104), of a stack comprising a first portion of semiconductor capable of forming an active area and disposed between two second portions of a material capable of being selectively etched with respect to the semi- driver of the first portion,
    b) making, on a part of the stack, external spacers (112) and a dummy grid,
    c) etching of the second portions such that the remaining portions are arranged under the dummy grid,
    d) partial oxidation of the remaining parts from external faces, forming internal spacers (118),
    e) removal of the dummy grid and non-oxidized parts of the remaining parts arranged under the dummy grid,
    f) production of a grid (128) between the external spacers and between the internal spacers and covering the channel.
    112 132 112 130 112 132 112
    i
    METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE WITH SPACERS
    SELF-ALIGNED INTERNS
    DESCRIPTION
    TECHNICAL AREA AND PRIOR ART
    The invention relates to a method for producing a semiconductor device comprising one or more transistors, for example of the GAA-FET type (“Gate-AII-Around Field Effect Transistor”, or field effect transistor with a covering grid), and internal spacers self-aligned with respect to each other.
    In a GAA-FET type transistor, the gate of the transistor is formed all around the channel such that the channel is surrounded or coated by the gate. The advantage of such a transistor, compared to a conventional MOSFET, is to improve the electrostatic control of the channel by the gate (which makes it possible to reduce the leakage currents), in particular when the transistor is completely deserted (for example of the type FDSOI, or “Fully-Depleted Silicon On Insulator).
    It is known to make a GAA-FET type transistor comprising a stack of several semiconductor nanowires together forming the transistor channel. This configuration makes it possible to obtain a good compromise between the electrostatic control of the channel by the gate and the control current required in the transistor.
    The addition of a constraint in the transistor channel contributes to the improvement of the performances of the transistor. This constraint is preferably uniaxial and parallel to the direction of movement of the charge carriers in the channel. A compression stress applied to the channel improves the mobility of the charge carriers in a P-type transistor, while a voltage stress will have a beneficial effect in a N-type transistor.
    Document US 2014/0054724 A1 describes a process for producing a GAA-FET transistor. In such a transistor, the electrical insulation between the gate and the source and drain regions is ensured by external spacers formed on the initial material stack used for producing the active area of the transistor, as well as by internal spacers. made within this stack. These internal spacers are necessary to reduce the capacitive effects between the gate and the source and drain regions. In this document, the internal spacers are produced by etching, in the semiconductor located against the nanowire (s) of the channel, one or more cavities intended to be vertically aligned with respect to the external spacers, then by producing oxidation of the semiconductor walls of the cavity or cavities formed. This or these cavities are then filled with the gate materials (dielectric + conductive material).
    The process described in this document however poses a problem. Indeed, since the cavity or cavities formed within the stack for the production of the internal spacers are obtained by etching without stop layer, the desired alignment between the internal edges of the external spacers and the side walls of the cavities is difficult to obtain because it depends on the duration of implementation of the engraving. In practice, the internal spacers obtained with this method are not precisely aligned either with the external spacers, or one above the other. This represents a source of variability in the electrical characteristics of a transistor thus produced, in particular because variations on the dimensions of the internal spacers directly influence the length of the channel.
    Document US 2014/0001441 A1 describes another method for producing a GAA-FET transistor. In this method, the production of the spacers includes the implementation of an etching, at the source and drain regions and up to under external spacers, of sacrificial layers located between the nanowires intended to form the channel regions, source and drain of the transistor. A material with particular properties is then deposited in the engraved spaces, then a step of transforming and / or engraving the portions of this material which are outside the locations provided for the internal spacers is then implemented so that the remaining parts of this material forms the internal spacers. The transistor is completed by forming the final gate of the transistor.
    Here again, the production of the cavities in which the internal spacers are formed implies the implementation of etching without a stop layer. The alignment sought between the channel region and the walls of the cavities is difficult to obtain. In practice, the internal spacers obtained are not precisely aligned either with the external spacers, or with the channel region, or with respect to each other. This represents a source of variability in the electrical characteristics of the transistor thus produced, in particular because the variations in the dimensions of the internal spacers directly influence the length of channel obtained. In addition, for the production of spacers, this process uses a particular material whose nature is not identifiable.
    STATEMENT OF THE INVENTION
    An object of the present invention is to provide a method for producing a semiconductor device suitable for producing a GAA-FET transistor and the internal spacers of which are produced in a self-aligned manner with respect to each other.
    For this, the present invention proposes a method for producing a semiconductor device, comprising at least the implementation of the following steps:
    a) production, on a substrate, of a stack comprising at least a first portion of semiconductor disposed between at least two second portions of at least one material capable of being selectively etched with respect to the semiconductor of the first portion, the first portion being capable of forming at least one active area of the semiconductor device;
    b) making, on a part of the stack, external spacers and at least one dummy grid disposed between the external spacers;
    c) etching of the second portions such that the remaining parts of the second portions are arranged at least under the dummy grid;
    d) partial oxidation of the remaining parts of the second portions from external faces of the remaining parts of the second portions revealed by the etching of the second portions, forming internal spacers;
    e) removing the dummy grid and non-oxidized parts from the remaining parts of the second portions disposed at least under the dummy grid;
    f) production of a grid between the external spacers and between the internal spacers, covering the channel and capable of being electrically isolated from source and drain regions by the external spacers and by the internal spacers.
    Thus, the surfaces from which the internal spacers are made correspond to the surfaces revealed by the etching of the second portions using the dummy grid, and possibly the external spacers, as an etching mask. Thus, these surfaces are aligned with respect to each other, which allows self-alignment of the internal spacers with one another, and with respect to the external spacers when the external spacers are present during the etching of the second portions. This self-alignment is obtained regardless of the number of first semiconductor portions used to make the channel.
    With such a method, the self-aligned production of the internal spacers does not modify the channel length of the semiconductor device and does not affect the electrical performance of the semiconductor device.
    The internal spacers correspond to the elements intended to electrically isolate the grid from the source and drain regions within the stack from which the semiconductor device is made. The internal spacers are disposed above and below the source and drain extension regions.
    The external spacers correspond to the elements intended to electrically isolate the grid from the source and drain regions above the stack from which the semiconductor device is made. The external spacers cover at least a portion of the source and drain extension regions.
    In addition, compared with internal spacers which would be produced by depositing material in cavities formed by etching, the use of oxidation to form the internal spacers has the advantage of reducing the processing constraints for the production of these internal spacers, such as for example the dimensions or the aspect ratio of the internal spacers that can be produced, since the production of internal spacers by deposition imposes constraints on the thickness of material deposited relative to the dimensions of the locations of the spacers internal. In addition, the production of internal spacers by deposition of a dielectric material also requires the implementation of a step of etching the dielectric material deposited outside the locations provided for the internal spacers. Such a removal step is not necessarily implemented when the internal spacers are produced by oxidation because oxide does not form on all the materials present.
    In addition, during the production of several devices very close to each other, the production of internal spacers via a deposition of dielectric material is problematic, unlike the production of internal spacers by oxidation.
    According to first and second embodiments, the method can be such that:
    - Etching step c) is implemented such that the remaining parts of the second portions are also arranged under the external spacers;
    - the internal spacers are arranged at least partially under the external spacers.
    In these first and second embodiments, the dummy grid and the external spacers together form an etching mask used to define the surfaces from which the internal spacers are formed by oxidation. Thus, the internal spacers formed can be arranged at least partially under the external spacers.
    In this case, the method can also comprise, between steps d) and e), producing the source and drain regions by semiconductor epitaxy from at least parts of the first portion of semiconductor.
    According to the first and second embodiments, the implementation of step c) can also etch the first portion of semiconductor such that a remaining portion of the first portion of semiconductor disposed at least under the dummy grid be kept.
    According to the second embodiment:
    - Step b) can be implemented such that at least two dummy grids are produced on the stack, each of the dummy grids being disposed between external spacers;
    - Step c) can be implemented such that at least part of the first portion of semiconductor located between the two dummy gates is not etched.
    Thus, the part of the first portion of semiconductor located between the two dummy gates can be used to form a continuous active zone for at least two transistors arranged one next to the other and sharing the same source region and drain (forming the source for one of the two transistors and the drain for the other transistor). In this configuration, properties of the semiconductor of the first portion (for example the presence of dopants and / or chemical components) can be used when producing the common source and drain region, for example to introduce a stress in the semiconductor of the source and drain region
    The addition of a constraint in the channel contributes to the improvement of the performances of the transistor. This constraint is preferably uni-axial and parallel to the direction of movement of the charge carriers in the channel. When the semiconductor device corresponds to an N-type transistor, this constraint can correspond to a voltage constraint applied to the channel, which makes it possible to improve the mobility of the charge carriers in the transistor. When the semiconductor device corresponds to a P-type transistor, this stress can correspond to a compression stress.
    According to a third embodiment:
    the method can also comprise, between steps b) and c), the implementation of a deposit of a protective material covering parts of the stack not covered by the dummy grid and by the external spacers, then a deletion, for example an engraving, of external spacers, called first external spacers;
    - The implementation of step c) also etches parts of the first portion of semiconductor previously arranged under the first external spacers;
    - The implementation of step d) also performs a partial oxidation of second remaining parts of the second portions covered by the protective material from external faces of the second remaining parts of the second portions revealed by the etching of the second portions;
    and the method can also comprise, between steps d) and e), the implementation of the following steps:
    - semiconductor epitaxy at least between a first part of the first semiconductor portion disposed under the dummy grid and second portions of the first semiconductor portion disposed under the protective material, forming extension regions source and drain and then
    - production of second external spacers at least on the source and drain extension regions, then
    - removal of the protective material and of the second parts of the second portions, then
    - Realization of the source and drain regions by semiconductor epitaxy from at least the second parts of the first portion of semiconductor.
    In this third embodiment, the method can also comprise, between the step of removing the protective material and the step of producing the source and drain regions, a step of removing at least part of the portions oxidized from the second portions covered by the protective material. On the other hand, these oxidized portions originating from the second portions covered by the protective material are advantageously preserved when cavities are present in the source and drain extension regions, under the external spacers.
    For all of the embodiments, the oxidation step d) can also carry out a partial oxidation of the first portion of semiconductor, the process possibly comprising, between steps d) and e), the implementation an etching of oxidized parts of the first portion of semiconductor.
    In addition, the material of the second portions may be able to oxidize more quickly than the semiconductor of the first portion. Thus, the impact on the first portion of the oxidation used to form the internal spacers is minimized. When the material of the second portions is capable of oxidizing faster than the semiconductor of the first portion, this oxidized portion of the first portion of the semiconductor can therefore be etched in order to limit the impact of the oxidation on the first portion of semiconductor.
    In this case, the semiconductor of the first portion can be silicon or SiGe, and the material of the second portions can be SiGe comprising a proportion of germanium greater than that of the semiconductor of the first portion.
    Thus, the difference in oxidation rate between the semiconductor of the first portion and that of the second portions can be advantageously obtained thanks to the difference in concentrations, or proportions, of germanium in the semiconductors (the one having the highest concentration germanium oxidizing faster than the other semiconductor).
    Advantageously, the semiconductor of the source and drain regions can be SiGe constrained in compression when the semiconductor device corresponds to a P-type transistor.
    The stack can comprise several first semiconductor portions each forming a nanowire disposed between two second portions.
    The semiconductor device advantageously comprises at least one GAA-FET transistor.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of exemplary embodiments given for purely indicative and in no way limiting, with reference to the appended drawings in which:
    FIGS. 1A to 1G represent the steps of a method for producing a semiconductor device, object of the present invention, according to a first embodiment,
    FIGS. 2A to 2D represent a part of the steps of a method for producing a semiconductor device, object of the present invention, according to a second embodiment,
    - Figures 3A to 31 show a part of the steps of a method for producing a semiconductor device, object of the present invention, according to a third embodiment.
    Identical, similar or equivalent parts of the different figures described below have the same reference numerals so as to facilitate the passage from one figure to another.
    The different parts shown in the figures are not necessarily shown on a uniform scale, to make the figures more readable.
    The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with one another.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    First of all, reference is made to FIGS. 1A to 1G which represent the steps of a method for producing a semiconductor device 100 here comprising two GAA-FET P-type transistors, according to a first embodiment.
    As shown in FIG. 1A, the device 100 is produced from a stack 102 of layers of different materials arranged on a substrate 104. In the first embodiment described here, the substrate 104 corresponds to a solid substrate, or " bulk ”, of semiconductor, for example silicon or SiGe. The stack 102 comprises layers 106, 108 of two different materials and arranged alternately one above the other. Each of the layers 108 is intended to form one or more semiconductor nanowires of one or more channels of the device 100 and is arranged between two layers 106 comprising a material ίο capable of being selectively etched relative to that of the layers 108. In the first embodiment described here, the stack 102 comprises three layers 108 as well as four layers 106 arranged in an alternating manner such that each of the layers 108 is disposed between two layers 106.
    As a variant, the substrate used can correspond to an SOI substrate (silicon on insulator), with in this case the reference 104 which designates the buried dielectric layer, or BOX (“Buried Oxide”) of the SOI substrate and the first layer 106 (that disposed against layer 104) which designates the surface layer, or thin layer, of the SOI substrate. . As a variant, the first layer 106 may correspond to a layer other than the surface layer of an SOI substrate, for example a layer of SiGe obtained by condensation.
    The term nanowire is used here to denote any portion of material of nanometric or even micrometric dimensions, and of elongated shape, whatever the shape of the section of this portion. Thus, this term designates as many portions of elongated material of circular or substantially circular section, but also portions of material in the form of beams or bars comprising for example a rectangular or substantially rectangular section.
    In the first embodiment described here, the layers 108 comprise silicon, and the layers 106 comprise SiGe with a proportion of germanium for example of between approximately 10% (Sio, 9Geo, i) and 80% (Sio, 2Geo, 8). The substrate 104 comprises a solid layer, for example made of silicon, on which is placed a layer of relaxed (also called SRB or “Strain Relaxed Buffer”) or strained SiGe.
    The stack 102 is engraved in the form of one or more elongated portions. The width of this or these portions (which corresponds to the dimension along the axis Y shown in FIG. 1A) is equal to the desired width of the nanowires of the device 100 which will be formed by the portions of the layers 108 obtained subsequently.
    One or more dummy grids 110 are then produced, for example by lithography and etching, on the elongated portion or portions formed from the stack 102, at the locations intended for the future grids of the device 100. In FIG. 1A, two dummy grids 110 are carried out. The dummy grids 110 are arranged above the parts of the layers 108 intended to form the nanowires, that is to say the channels of the device 100, and of the parts of the layers 106 between which these parts of the layers 108 are located, and also cover lateral flanks of these parts of layers 108 and 106.
    External spacers 112 are then produced, for example by deposition and etching, on the stack 102, and against the lateral flanks of the dummy grid 110. These external spacers 112 are notably arranged above parts of the layers 108 intended to be find in the source and drain extension regions, that is to say between the channel and the source and drain regions of the device 100. The length, or depth, of these external spacers 112 (dimension parallel to l X axis shown in Figure IA) is for example between about 3 and 8 nm.
    The parts of the stack 102 not covered by the dummy grid 110 and by the external spacers 112 are then etched, forming the structure shown in FIG. 1B. The remaining portions of the layers 108 form nanowires 114 of the device 100. Each of the nanowires 114 is interposed between two remaining portions 116 of the layers 106.
    In this first embodiment, internal spacers of the device 100 are intended to be produced by oxidation of part of the remaining portions 116, from the external faces of these portions 116 revealed by the previous etching implemented using the dummy grids 110 and the external spacers 112 as an etching mask. The oxidized portions obtained are intended to form internal spacers ensuring, with the external spacers 112, the isolation of the grids with respect to the source and drain regions.
    This oxidation will also impact the semiconductor of the nanowires 114. So that the implementation of this oxidation does not transform into oxide all of the semiconductor of the nanowires 114, the material of the portions 116 (and therefore that of the layers 106). is chosen such that its oxidation speed is greater than that of the material of the nanowires 114 (and therefore of the layers 108). Thus, in the embodiment described here, this property is obtained by the production of layers 108 of silicon and layers 106 of SiGe with a germanium concentration of, for example, between approximately 30% and 60%.
    The higher the germanium concentration in the SiGe of the portions 116, the faster this semiconductor will oxidize compared to the semiconductor of the nanowires 114, and / or the lower the temperature at which the oxidation is carried out. Significant selectivity in particular gives greater latitude in the choice of the duration and the temperature for carrying out the oxidation.
    A partial oxidation of the portions 116, from the surfaces forming the lateral flanks of the structures obtained by the implementation of the previous etching, is then implemented. This oxidation forms, at the level of the future source and drain extension regions (that is to say under the external spacers 112), internal spacers 118 comprising a dielectric material and intended to isolate the source and drain vis-à-vis the grid which will be made later (Figure IC).
    The length, or depth (dimension parallel to the X axis), of each internal spacer 118 is here substantially equal to that of each external spacer 112 so that in the rest of the process, the external 112 and internal spacers 118 are aligned with respect to to the grid.
    During this oxidation, part of the nanowires 114 oxidizes. The oxidized portions of nanowires 114 are designated in FIG. 1C by the reference 120. However, due to the materials used (nanowires 114 in silicon and source and drain regions 118, 120 in SiGe), the oxidation of nanowires 114 is more slow than that of the portions 116. In the first embodiment described here, this difference in oxidation speed is due to the high germanium concentration in the portions 116 which allows oxidation of the SiGe faster than that of the silicon of the nanowires 114 For example, considering SiGe whose germanium concentration is equal to approximately 50% (Sio, 5Geo, 5) and an oxidation forming an oxide of thickness equal to approximately 10 nm, the oxide thickness obtained by the implementation of this oxidation on silicon is between approximately 1 nm and 6 nm (thickness varying in particular depending on whether a native oxide is present on the surface of the silicon of the nanowires 114, or whether the nanowires 114 have previously undergone deoxidation, p ar example with a HF solution, removing this native oxide).
    Preferably, this oxidation is carried out at a low temperature of between approximately 700 ° C and 900 ° C, for example less than approximately 850 ° C, in order to accentuate the oxidation selectivity obtained thanks to the different compositions of the exposed materials. oxidation processes.
    In certain cases, higher temperatures can however be envisaged since an increase in the temperature for carrying out the oxidation allows faster oxidation of the materials. For example, by carrying out the oxidation at a temperature of approximately 1100 ° C. on Sio, sGeo, 5, an oxide thickness of approximately 8 nm is obtained after 1 second of oxidation, the thickness d oxide formed on silicon being 4 nm for the same oxidation time.
    This oxidation is, for example, a plasma-assisted oxidation or a dry oxidation in the presence of oxygen, or else annealing in an oxidizing atmosphere.
    The parameters for implementing this oxidation are preferably chosen such that the interfaces between the internal spacers 118 formed and the remaining portions 116 are substantially aligned with the interfaces between the external spacers 112 and the dummy grids 110, that is to say say that the interior flanks of the internal spacers 118 are aligned with respect to the interior flanks of the external spacers 112. Furthermore, these interfaces of the internal spacers 118 are self-aligned with respect to each other and aligned one above the other. others due to the fact that the internal spacers 118 are formed by the same oxidation step of the portions 116 which comprise the same material.
    In the first embodiment described here, since the material of the substrate 104 on which the stack 102 is located is SiGe, part 122 of the thickness of SiGe 104 is also transformed into oxide. The thickness of the part 122 is a function in particular of the nature of the material undergoing oxidation, and in particular here a function of the germanium concentration of the SiGe. Such oxidation also occurs when the substrate 104 comprises silicon.
    Then, the oxidized portions 120 formed at the ends of the nanowires 114 are removed by etching. When germanium oxide is removed, it is possible to implement a method as described in the document “Selective GeOx-Scavenging from Interfacial Layer on Sii-xGex Channel for High Mobility Si / Sii-xGex CMOS Application” CH Lee et al., 2016 Symposium on VLSI Technology Digest of Technical Papers, pages 36-37.
    This etching also impacts the semiconductor oxide of the internal spacers 118 and the oxide formed in the substrate 104, and therefore also removes a similar thickness of oxide from the internal spacers 118 and of the substrate 104 (FIG. 1D). At the end of this etching, the ends of the nanowires 114 are no longer covered by oxide, and the internal spacers 118 have a length, or depth, typically corresponding to the difference between the initial length of the internal spacers 118 and l 'thickness of oxide removed formed on the ends of the nanowires 114, and for example between about 1 nm and 2.5 nm.
    Thus, owing to the fact that the internal spacers 118 have been formed by implementing the same oxidation step and that the thickness of oxide subsequently removed is similar for all the internal spacers 118, the internal spacers 118 obtained at the results of these steps are well aligned with each other.
    As shown in FIG. 1E, source and drain regions 124 are then formed by epitaxy on the substrate 104, from the ends of the nanowires 114. These regions 124 are produced with in-situ doping so as to obtain a good quality of junction. For example, the doping of the material of the regions 124 can be carried out with boron doping atoms whose concentration is for example between approximately 10 18 and 10 21 at / cm 3 . The material of the source and drain regions 124 is, for example, SiGe: B or Si: B. In addition, in the first embodiment described here, the two GAA-FET transistors of the device 100 include a source region and common drain 124 forming for one of the two transistors a source region, and for the other of the two transistors a drain region.
    At this stage, the internal spacers 118 are interposed between the source and drain regions 124 and the portions 116.
    In the first embodiment described here, the source and drain regions 124 comprise Si or SiGe. The germanium concentration of SiGe in the source and drain regions 124 is for example between approximately 20% (Sio, 8Geo, 2) and 80%. (Sio, 2Geo, 8). In general, in a P-type transistor, the germanium concentration in the semiconductor of the source and drain regions 124 can be higher than that in the semiconductor of nanowires 114.
    Encapsulation material 126 is then deposited on the source and drain regions 124 so as not to alter these regions during the implementation of the subsequent steps.
    The dummy grid 110 is then etched, revealing the nanowires 114 and also forming accesses to the portions 116. Selective etching of the remaining portions 116 with respect to the nanowires 114, internal spacers 118 and external spacers 112 is then put in place. work to release the nanowires 114 forming the channels of the device 100 (Figure 1F). This etching corresponds for example to a chemical etching HCI / H2. This engraving reveals the self-aligned walls with respect to each other of the internal spacers 118.
    Grids 128, comprising at least one grid dielectric and a grid conductive material, are then produced between the external spacers 112 and the internal spacers 118, at the locations previously occupied by the dummy grids 110. The grids 128 thus produced surround the nanowires 114 and are electrically isolated from the source and drain regions 124 by the internal spacers 118.
    Thus, the internal spacers 118 make it possible to reduce the capacitive effects between the grids 128 and the source and drain regions 124.
    The device 100 is completed by removing the encapsulation material 126 and by forming electrical contacts 130 and 132 on the source and drain regions 124 and on the grid 128 (FIG. 1G).
    In the first embodiment described above, part of the material of the substrate 104 exposed to oxidation is transformed into oxide. As a variant, it is possible that the substrate corresponds to an SOI (silicon on insulator) substrate, with in this case the reference 104 which designates the buried dielectric layer, or BOX (“Buried
    Oxide ”) of the SOI substrate and the first layer 106 (the one placed against the layer 104) which designates the surface layer, or thin layer, of the SOI substrate. In this variant, the layer 122 does not form in the substrate 104 during the oxidation carried out because the material of the substrate exposed to the oxidation is oxide. In general, it is possible to use a substrate 104 whose material is not liable to oxidize, and no part of the substrate 104 is in this case transformed into oxide.
    In a variant of this first embodiment, when the substrate 104 corresponds to a silicon substrate, the thickness of the layer 122 formed is much smaller than in the case of a substrate 104 comprising SiGe.
    According to a variant of the method described above, it is possible to implement first of all the steps described in connection with Figures IA and IB. Then, it is possible to selectively etch the portions 116 with respect to the other materials present (this selective etching being possible thanks to the fact that the germanium concentration in the semiconductor of the layers 106 is higher than that in the semiconductor layers 108), then forming cavities between which the nanowires 114. Are located A material capable of being selectively etched with respect to the nanowires 114, the future internal spacers and the external spacers 112, is then deposited in these cavities, forming portions between which the nanowires 114 are arranged. Thus, the material of the initial stack located between the nanowires 114 is replaced by another material. This variant can therefore be implemented when the desired material between the nanowires 114 cannot be obtained during the production of the initial stack of layers 106, 108. This replacement material corresponds for example to a semiconductor such as SiGe with a high concentration of germanium, or germanium. For example, when the source and drain regions of the device 100 are intended to be produced subsequently in SiGe, the germanium concentration in the SiGe which corresponds to this replacement material may be at least 20% higher than that of SiGe from source and drain regions. In this case, the portions of this replacement material can be formed via a selective deposition process such that this material is deposited only around the nanowires 114, or else by an anisotropic RIE deposition and etching. The process is then completed by implementing the steps previously described in connection with Figures IC to IG.
    According to another alternative embodiment, it is possible that the source and drain regions 124 are obtained by implementing several epitaxies allowing the growth of materials of different compositions (for example by varying the concentration of germanium between the epitaxies) and / or different dopant concentrations. For example, the production of the source and drain regions 124 may include the implementation of a first epitaxy of SiGe comprising carbon atoms, then of a second epitaxy of SiGe not comprising carbon atoms. Thus, because the epitaxy is implemented with in situ doping of the source and drain regions 124 formed, the portion of SiGe comprising carbon atoms formed initially makes it possible to reduce the diffusion of dopants in the channel regions of device 100.
    The characteristics of the oxidation used can also be a function of the crystalline orientation of the semiconductors used, as described for example in the document "The Effect of Surface Orientation on Silicon Oxidation Kinetics" by EA Lewis et al., J Electrochem. Soc. 1987, vol. 134, issue 9, pp. 23322339.
    Indeed, the oxidation of a crystal orientation face (110) is faster than that of a crystal orientation face (100). Thus, the main surfaces, or the majority of the perimeter, of the channel, which correspond to orientation surfaces (100) are oxidized less quickly than those of orientation (110) where the internal spacers are made.
    Thus, two oxidation selectivity parameters are used in this process for the production of internal spacers: the composition of the oxidized material and the crystallography of the oxidized material.
    A method of producing the device 100 according to a second embodiment is described in connection with FIGS. 2A to 2D.
    The initial stack 102 used in this second embodiment is similar to that used in the first embodiment.
    The steps previously described in connection with Figures IA and IB are first implemented. However, unlike the first embodiment in which the nanowires 114 are interrupted between two transistors, the etching of the stack 102 used is such that the nanowires 114 of the two transistors are here formed by continuous portions which are not interrupted at the level of the future common source and drain region intended to be produced for these two transistors. The structure obtained is shown in Figure 2A.
    As for the first embodiment described above, a partial oxidation of the portions 116, from the surfaces forming the lateral flanks of the structures obtained by the implementation of the previous etching, is then implemented, forming the internal spacers 118.
    In addition, part of the nanowires 114 oxidizes. Thus, oxidized portions 120 are formed at the ends of the nanowires 114.
    Since the nanowires 114 are not interrupted between the transistors, the parts of the nanowires 114 present at the level of the future common source and drain region are also partially oxidized, forming the oxide portions referenced 202 in FIG. 2B. These oxide portions 202 surround parts 204 of the nanowires 114 which have not been transformed into oxide.
    Unlike the substrate 104 used in the first embodiment, the material of the substrate 104 used in this second embodiment is not liable to oxidize, and no part of the substrate 104 is transformed into oxide. Alternatively, it is however possible to use a substrate 104 capable of oxidizing, as previously described for the first embodiment.
    The parameters for implementing this oxidation can be similar to those previously described for the first embodiment.
    The oxidized portions 120 and 202 formed around the nanowires 114 are removed by etching which also removes a similar thickness of oxide from the internal spacers 118.
    As before, since the internal spacers 118 were formed by the implementation of the same oxidation step and the thickness of oxide then removed is similar for all the internal spacers 118, the internal spacers 118 obtained at the end of these steps are self-aligned with respect to each other.
    As shown in FIG. 2C, source and drain regions 124 are produced via the implementation of an epitaxy. These regions 124 are advantageously produced with in situ doping so as to obtain a good quality of junction. For example, the doping of the material of the regions 124 can be carried out with boron doping atoms whose concentration is for example between approximately 10 18 and 10 21 at / cm 3 . The material of the source and drain regions 124 is for example SiGe: B for a P-type transistor, or a material with a lattice parameter lower than that of silicon in order to introduce a voltage stress in the case of an N-type transistor, such as Si: C (1%).
    In this second embodiment described here, the parts 204 of the nanowires 114 present at the level of the source and drain region common to the two transistors also contribute to the growth by epitaxy of SiGe of this common region of source and drain. In addition, the presence of these parts 204 brings a constraint in the channel region, thus improving the electrical characteristics of the transistor.
    Advantageously, diffusion of the germanium present in the semiconductor of the parts 204 is implemented in order to increase the stress within the common source and drain region. This diffusion is obtained by implementing a suitable thermal annealing.
    The structure obtained after this diffusion is shown in Figure 2D.
    The method according to this second embodiment is completed in a similar manner to the first embodiment, that is to say by depositing an encapsulation material on the source and drain regions 124, by etching the dummy grids 110 and the portions 116, by making the final grids and then the electrical contacts of the transistors.
    The different variants previously described for the first embodiment can be applied to the second embodiment.
    A method of producing the device 100 according to a third embodiment is described in connection with FIGS. 3A to 31. In these figures, the production of a single GAA-FET transistor is described.
    The initial stack 102 used in this third embodiment is similar to that used in the first and second embodiments.
    As in the first and second embodiments described above, the stack 102 is first of all engraved in the form of one or more elongated portions (a single elongated portion being shown in FIG. 3A), then a dummy grid 110 and temporary external spacers 301 are then produced on the elongated portion formed from the stack 102, without subsequent etching of the parts of the stack 102 not covered by the temporary external spacers 301.
    An encapsulation material 303 is then deposited on the parts of the layers 106, 108 at the level of which the future source and drain regions of the transistor will be produced (FIG. 3A).
    As shown in FIG. 3B, the temporary external spacers 301 as well as the parts of the layers 106, 108 covered by the temporary external spacers 301 are etched, for example by RIE etching (reactive ion etching). This etching forms accesses to the remaining parts 116 of the layers 106 from which the internal spacers 118 are intended to be produced. This etching also defines the nanowires 114 intended to form the channel region of the transistor, as well as the remaining parts 116 of the layers 106 between which the nanowires 114 are arranged. The remaining parts of the layers 106, 108 covered by the encapsulation material 303 are referenced 302 and 304.
    Partial oxidation of the portions 116, from the surfaces forming the lateral flanks of the portions 116 and revealed by the previous etching, is then implemented, forming the internal spacers 118. This oxidation also impacts the remaining parts 302 from the surfaces forming the flanks lateral of these remaining parts 302 and revealed by the previous etching, and forms oxidized portions 306 arranged opposite the internal spacers 118 (FIG. 3C).
    A controlled deoxidation step is then carried out in order to remove the oxide formed on the surface of the silicon of the nanowires 114.
    As shown in FIG. 3D, an epitaxy is implemented to form source and drain extension regions 308, from the ends of the nanowires 114. Advantageously, the semiconductor of the regions 308 is doped. In the embodiment shown in FIG. 3D, the epitaxy is implemented such that the regions 308 formed fill all of the space freed up by the etching of the parts of the layers 106, 108 previously covered by the temporary external spacers 301, that is to say the space between the remaining parts 114, 116 and the remaining parts 302, 304 of the layers 106, 108.
    According to a first variant of this third embodiment, the epitaxy forming the extension regions 308 can be stopped as soon as the semiconductor portions formed by this epitaxy connect the nanowires 114 to the remaining portions 304 which lie opposite the nanowires 114. In this variant shown in FIG. 3E, the epitaxy is implemented such that the regions 308 formed partially fill the space freed up by the etching of the parts of the layers 106, 108 previously covered by the temporary external spacers 301. Remaining spaces are therefore located opposite the remaining parts 116 and 302 of the layers 106.
    Whether the extension regions completely or partially fill the space freed up by the etching of the parts of the layers 106, 108 previously covered by the temporary external spacers 301, the final external spacers 112 are produced on and around the extension regions 308.
    In the case of extension regions 308 produced as shown in FIG. 3E, a part of the material of the external spacers 112 can be deposited between the semiconductor portions forming the extension regions 308. This configuration is shown in Figure 3F. It is also possible that the material of the external spacers 112 is deposited such that it remains localized above the extension regions 308. In this case, cavities 310 are present between the extension regions 308, allowing obtaining better electrical insulation. This configuration is shown in Figure 3G.
    The encapsulation material 303 is then removed, then the remaining parts 302 from the layers 106 are removed by etching. During this etching, the oxidized portions 306 protect the material from the extension regions 308 from the etching agents used (FIG. 3H, which corresponds to the configuration where the material of the external spacers 112 is present between the portions of the extension regions 308).
    In the absence of the cavities 310, the oxidized portions 306 can be eliminated.
    The source and drain regions 124 are then produced by epitaxy from the semiconductor surfaces of the portions 304 (FIG. 31). The semiconductor of the source and drain regions is advantageously SiGe comprising a germanium concentration greater than or equal to about 35% and doped with boron atoms, or else silicon doped with phosphorus atoms.
    The production of the device 100 is then completed by depositing the encapsulation material 126 on the source and drain regions 124, by etching the dummy grid 110, by etching the portions 116, by producing the grid 128, then by removing the material encapsulation 126 and forming the electrical contacts 130, 132, as previously described for the previous embodiments.
    The variants previously described for the first and second embodiments can be applied to this third embodiment.
    权利要求:
    Claims (13)
    [1" id="c-fr-0001]
    1. Method for producing a semiconductor device (100), comprising at least the implementation of the following steps:
    a) production, on a substrate (104), of a stack (102) comprising at least a first portion (108) of semiconductor disposed between at least two second portions (106) of at least one material capable of being selectively etched with respect to the semiconductor of the first portion (108), the first portion (108) being capable of forming at least one active area of the semiconductor device (100),
    b) making, on a part of the stack (102), external spacers (112, 301) and at least one dummy grid (110) disposed between the external spacers (112, 301),
    c) etching of the second portions (106) such that the remaining portions (116) of the second portions (106) are arranged at least under the dummy grid (110),
    d) partial oxidation of the remaining parts (116) of the second portions (106) from external faces of the remaining parts (116) of the second portions (106) revealed by the etching of the second portions (106), forming internal spacers (118) ,
    e) removing the dummy grid (110) and non-oxidized parts of the remaining parts (116) of the second portions (106) disposed at least under the dummy grid (110),
    f) production of a grid (128) between the external spacers (112) and between the internal spacers (118), covering the channel and capable of being electrically isolated from source and drain regions (124) by the external spacers ( 112) and the internal spacers (118).
    [2" id="c-fr-0002]
    2. Method according to claim 1, in which:
    the etching step c) is implemented such that the remaining parts (116) of the second portions (106) are also arranged under the external spacers (112),
    - the internal spacers (118) are arranged at least partially under the external spacers (112).
    [3" id="c-fr-0003]
    3. Method according to one of the preceding claims, further comprising, between steps d) and e), producing the source and drain regions (124) by semiconductor epitaxy from at least parts (114) of the first semiconductor portion (108).
    [4" id="c-fr-0004]
    4. Method according to one of the preceding claims, in which the implementation of step c) also etches the first portion of semiconductor (108) such as a remaining portion (114) of the first portion of semi -conductor (108) disposed at least under the dummy grid (110) is kept.
    [5" id="c-fr-0005]
    5. Method according to one of the preceding claims, in which:
    step b) is implemented such that at least two dummy grids (110) are produced on the stack (102), each of the dummy grids (110) being disposed between external spacers (112),
    - Step c) is implemented such that at least part of the first portion of semiconductor (108) located between the two dummy grids (110) is not etched.
    [6" id="c-fr-0006]
    6. Method according to claim 1, in which:
    - the method further comprises, between steps b) and c), the implementation of a deposit of a protective material (303) covering parts of the stack (102) not covered by the dummy grid ( 110) and by the external spacers (301), then a deletion of the external spacers (301), called the first external spacers,
    the implementation of step c) also etches parts of the first portion of semiconductor (108) previously placed under the first external spacers (301),
    - The implementation of step d) also performs a partial oxidation of second remaining parts (302) of the second portions (106) covered by the protective material (303) from external faces of the second remaining parts (302) of the second portions (106) revealed by the etching of the second portions (106), and further comprising, between steps d) and e), the implementation of the following steps:
    - semiconductor epitaxy at least between a first part (114) of the first semiconductor portion (108) disposed under the dummy grid (110) and second parts (304) of the first semiconductor portion ( 108) arranged under the protective material (303), forming source and drain extension regions (308), then
    - production of second external spacers (112) at least on the source and drain extension regions (308), then
    - Removal of the protective material (303) and the second remaining parts (302) from the second portions (106), then
    - Realization of the source and drain regions (124) by semiconductor epitaxy from at least the second parts (304) of the first portion of semiconductor.
    [7" id="c-fr-0007]
    7. The method of claim 6, further comprising, between the step of removing the protective material (303) and the step of producing the source and drain regions (124), a step of removing at least a portion of oxidized portions (306) from the second portions (106) covered by the protective material (303).
    [8" id="c-fr-0008]
    8. Method according to one of the preceding claims, in which the oxidation step d) also performs a partial oxidation of the first portion of semiconductor (108), the method further comprising, between steps d) and e), the implementation of etching of oxidized parts (120) of the first portion of semiconductor (108).
    [9" id="c-fr-0009]
    9. Method according to one of the preceding claims, in which the material of the second portions (106) is capable of oxidizing more quickly than the semiconductor of the first portion (108).
    10. The method of claim 9, wherein the semiconductor of the first portion (108) is silicon or SiGe, and the material of the second portions (106) is SiGe having a proportion of germanium greater than that of semiconductor of the first portion (108).
    [10" id="c-fr-0010]
    10
    [11" id="c-fr-0011]
    11. Method according to one of claims 3 and 6, in which the semiconductor of the source and drain regions (124) is SiGe constrained in compression when the semiconductor device (100) corresponds to a P-type transistor.
    [12" id="c-fr-0012]
    12. Method according to one of the preceding claims, in which
    15 the stack (102) comprises several first portions (108) of semiconductor each forming a nanowire (114) disposed between two second portions (116).
    [13" id="c-fr-0013]
    13. Method according to one of the preceding claims, in which the semiconductor device (100) comprises at least one GAA-FET transistor.
    S.60744
    1/11 ► N
    110 112 112 110
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    2018-06-22| PLSC| Publication of the preliminary search report|Effective date: 20180622 |
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1662531A|FR3060840B1|2016-12-15|2016-12-15|METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED INTERNAL SPACERS|
    FR1662531|2016-12-15|FR1662531A| FR3060840B1|2016-12-15|2016-12-15|METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED INTERNAL SPACERS|
    US15/837,405| US10217842B2|2016-12-15|2017-12-11|Method for making a semiconductor device with self-aligned inner spacers|
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